Operational amplifier

ABSTRACT

An operational amplifier comprises an initial amplifier stage having a pair of inputs, and a second amplifier stage connected to an output of the initial stage. A phase compensating capacitive element is connected between an output terminal of the second stage and a virtual ground point, and a constant current source is connected to the virtual ground point and the output of the initial stage. A resistive element and a capacitive element are series-connected between the output of the initial stage and the output of the second stage.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to operational amplifiers, and more specifically to operational amplifiers having a phase compensating circuit.

2. Description of Related Art

At present, operational amplifiers are widely used in various fields, particularly as one important element in analog circuits. Ordinarily, the operational amplifier fundamentally comprises two amplifier stages, i.e., an initial amplifier stage having an inverted input and a non-inverted input, and an output amplifier stage having an input connected to an output of the initial stage. This output stage ordinarily includes a capacitive feedback circuit between the output and the input of the output stage. However, in the case that the feedback path is established by only a simple capacitive electrical part, the gain of the operational amplifier does not sufficiently drop at a higher frequency region. This will often give rise to a problem of null or zero points, which lead to a cause for oscillation of the operational amplifier.

In order to avoid such an adverse effect of the zero points, various types of zero point compensating circuits have heretofore been proposed. However, almost the conventional zero point compensating circuits will make worse the supply voltage rejection ratio (abbreviated "SVRR" hereinafter) of the operational amplifier.

Among such conventional amplifiers having the zero point compensating circuits, one amplifier has succeeded not only in enabling the zero-point compensation but also in improving the SVRR, by forming the feedback circuit by series-connected capacitor and active load. In this amplifier, however, the active load is required to have a large transconductance, which will result in increase of power comsuption or increase in the element dimensions necessary for the active load, leading to increase in the integrated circuit chip size.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide an operational amplifier which is free from the above mentioned drawbacks in the conventional aamplifiers.

Another object of the present invention is to provide an operational amplifier associated with a phase compensating circuit having an excellent zero point compensating characteristics and an improved supply voltage rejection ratio.

Still another object of the present invention is to provide such an operational amplifier having a small power comsuption and a small required chip area.

The above and other objects of the present invention are achieved by an operational amplifier which comprises an initial amplifying stage having a pair of inputs, a second amplifying stage connected to an output of the initial stage, a phase compensating feedback capacitive element connected between an output terminal of the second amplifying stage and a virtual ground point, and a constant current source connected to the virtual ground point and the output of the initial stage. In accordance with the present invention, a resistive element and a second capacitive element are series-connected between the output of the initial stage and the output of the second stage.

The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing one conventional operational amplifier;

FIG. 2 is a graph showing the relation between the gain and frequency in the conventional operational amplifier shown in FIG. 1;

FIG. 3 is a view similar to FIG. 1 but showing another conventional operational amplifier;

FIG. 4 is a view similar to FIG. 1 but showing still another conventional amplifier;

FIGS. 5 and 6 are equivalent circuit diagrams of the amplifier shown in FIG. 4;

FIG. 7 is a fundamental circuit diagram illustrating the principle of the operational amplifier in accordance with the present invention;

FIGS. 8 and 9 are a small-signal equivalent circuit diagrams of the amplifier shown in FIG. 7; and

FIG. 10 is a circuit diagram showing one embodiment of the operational amplifier in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, there is shown a circuit diagram of a typical operational amplifier, which includes an initial stage constituted of a pair of input field effect transistors (abbreviated "FET" hereinafter) M₁ and M₂ connected to form a differential circuit. Therefore, a gate of the FET M₁ provides one input, for example, an inverted input of the operational amplifier, and a gate of the other FET M₂ functions the other input, for example, a non-inverted input of the amplifier. The pair of input FETs M₁ and M₂ have their drains respectively connected to a negative supply voltage through another pair of FETs M₃ and M₄ arranged to form an active load in the type of a current mirror circuit. Therefore, the FET M₂ forms a drain follower. Sources of the FETs M₁ an M₂ are common-connected to a drain of an FET M₅ whose source is connected to a positive supply voltage.

The drain of the FET M₂ is connected to a gate of an output FET M₆ which constitutes a second or output stage of the operational amplifier. This FET M₆ is connected at its source to the negative supply voltage and at its drain to the positive supply voltage through an FET M₇. In addition, the drain of the FET M₆ is connected through a phase compensating feedback capacitor C_(c) to the gate of the FET M₆ itself, and forms an output of the operational amplifier.

Gates of the FETs M₅ and M₇ are connected to a gate and a drain of an FET M₈ so as to form a current mirror circuit. The drain of the FET M₈ is connected to a constant current source I, so that the current flowing through the FET M₈ is defined by the constant current source I, and further, the respective currents flowing through the FETs M₅ and M₇ are controlled by the FET M₈.

Reviewing the above mentioned operational amplifier, it has the frequency characteristics as shown in FIG. 2. Namely, the gain does not drop at a high frequency, and therefore, an adverse effect of zero points often becomes a problem. For example, one adverse effect of zero points is to cause an oscillation of the operational amplifier.

Under the circumstances, there have been proposed various compensating circuits capable of eliminating the adverse effects of the zero point. However, almost the conventional zero point compensating circuits have rather adversely increased the SVRR.

One typical example of such conventional zero point compensating circuits will be now explained with reference to FIG. 3, showing a circuit diagram of a typical operational amplifier provided with such a zero point compensating means. In FIG. 3, circuit elements similar to those shown in FIG. 1 are given the same Reference Signs, and explanation will be omitted.

As seen from comparison between FIGS. 1 and 3, the operational amplifier shown in FIG. 3 comprises an FET M₉ connected between the gate of the output FET M₆ and the phase compensating feedback capacitor C_(c). The FET M₉ has a gate connected to the positive supply voltage, so that the capacitor C_(c) and the conductive resistance of the FET M₉ are series-connected to form a feedback loop which constitutes a zero point compensating circuit.

However, as mentioned above, since the gate of the FET M₉ is connected to the positive supply voltage, flactuation in the positive supply voltage will directly lead to variation in the gate-source voltage of the output FET M₆, which results in change of the output voltage. Namely, the SVRR is adversely increased.

Thus, in order to enable the zero point compensation and at the same time to improve the SVRR, one operational amplifier has been disclosed by B. K. Ahuja, "An Improved Frequency Compensation Technique for CMOS Operational Amplifiers" IEEE J. Solid-Stage Circuits, 1983 vol. sc-18, No. 6, pp 629-633. FIG. 4 shows a circuit diagram of the operational amplifier.

This operational amplifier comprises includes an initial stage constituted of a pair of input FETs M₁₁ and M₁₂ connected in the form of a differential circuit. A gate of the FET M₁₁ is connected to one input, for example, a non-inverted input of the operational amplifier, and a gate of the other FET M₁₂ is connected to the other input, for example, an inverted input of the amplifier. The pair of input FETs M₁₁ and M₁₂ have their drains respectively connected through FETs M₁₅ and M₁₆ to another pair of FETs M₁₃ and M₁₄ arranged to form an active load in the type of a current mirror circuit. Sources of the FETs M₁₁ and M₁₂ are common-connected to a drain of an FET M₁₇ whose source is connected to a positive supply voltage. Thus, the FET M₁₂ forms a drain follower, and the connection between the FETs M₁₄ and M₁₆ is connected to a gate of an output FET M₁₈ which constitutes a second or output stage of the operational amplifier.

This FET M₁₈ is connected at its source to a negative supply voltage and at its drain to the positive supply voltage through an FET M₁₉ which functions as an active load. In addition, the drain of the FET M₁₈ is connected to an output of the operational amplifier, and also connected through a phase compensation feedback capacitor C_(c) to a source of a gate-grounded FET M₂₀. This FET M₂₀ is connected at its drain to the gate of the FET M₁₈ and a drain of an FET M₂₁ whose source is connected to the negative supply voltage. Further, the source of the FET M₂₀ is connected through an FET M₂₂ to the positive supply voltage.

A constant current source I and an FET M₂₃ are connected in series across the supply voltages. The FET M₂₃ has a gate thereof connected to the drain of FET M₂₃ itself and also connected to gates of an FET M₂₄, the FET M₁₇ and the FET M₂₂, so that the FET M₂₃ constitutes an input path of a current mirror circuit and the FETs M₂₄, M₁₇ and M₂₂ form different output paths of the current mirror circuit, respectively. Further, the gate of the FET M₂₃ is connected to a gate of the FET M₁₉ through an FET M₂₅ having a gate connected to the negative supply voltage. In addition, the FET M₂₄ has a drain thereof connected through a gate-grounded FET M₂₆ to a gate and a drain of an FET M₂₇, whose source is connected to the negative supply voltage. This FET M₂₇ has its gate connected to gates of an FET M₂₈ and the FET M₂₁ so as to form a current mirror circuit having two output paths. The FET M₂₈ is connected at its drain to a source of a drain-grounded FET M₂₉ whose gate is connected to the gates of the FETs M₁₅ and M₁₆.

As seen from the above explanation, a zero point compensation circuit is formed by a closed loop starting from the drain of the FET M₁₈ and extending through the capacitor C_(c) and the drain-source path of the gate-grounded FET M₂₀ to the gate of the FET M₁₈.

In the B. K. Ahiya paper, a small-signal equivalent circuit shown in FIG. 5 was introduced from the operational amplifier shown in FIG. 4. In the equivalent circuit of FIG. 5, g_(m1) and g_(m2) represent the transconductances of the initial stage FET and the second stage FET, respectively. R₁ and C₁ designate output resistance and capacitance of the initial stage, and R₂ and C₂ show output resistance and capacitance of the second stage. V_(i) and V_(o) are input and output voltages, respectively. In addition, since one electrode "a" of the phase compensating capacitor C_(c) is connected to the source of the gate-grounded FET M₂₀ in the operational amplifier shown in FIG. 4, the electrode terminal "a" becomes a virtual ground point. Further, all the current flowing through the phase compensating capacitor C_(c) is flowed into the output terminal of the initial stage.

Thus, the current flowing from the output terminal of the initial stage through the phase compensating capacitor C_(c) to the output terminal of the second stage is canceled by the above current, so that the generation of a zero-point is prevented. Further, since the output terminal of the second stage is connected through the phase compensating capacitor to a low impedance point such as one terminal of the FET M₂₀, an excellent SVRR can be obtained.

In the circuit analysis as mentioned above, such an ideal case is assumed that the source of the gate-grounded FET M₂₀ is virtually grounded. In fact, however, the voltage at the source of the FET M₂₀ will fluctuate dependently upon variation in voltage at the output terminal of the second stage. The reason for this is that the source of the FET M₂₀ is actually connected to the ground point through a resistive component r_(m0) which is an inverted value of the transconductance g_(m0) of the FET M₂₀. Therefore, the small-signal equivalent circuit of the FIG. 4 operational amplifier should be corrected as shown in FIG. 6.

In the equivalent circuit shown in FIG. 6, the closed loop gain V_(o) /V_(i) to frequency S can be expressed as follows: ##EQU1## where V_(i) is an input voltage

V_(o) is an output voltage

A₁ =g_(m1) R₁, A₂ =g_(m2) R₂

b=R₁ C₁ +R₂ C₂ +R₂ C_(c) +r_(m0) C_(c) +A₂ R₁ C_(c)

c=R₁ R₂ C₁ (C_(c) +C₂)+r_(m0) R₂ C₂ C_(c)

d=r_(m0) R₁ R₂ C₁ C₂ C_(c)

As seen from the above equation (1), the operational amplifier of FIG. 4 has one zero point Z at the frequency S_(z) =-g_(m0) /C_(c). Therefore, in order to avoid the adverse effect of this zero point, it is necessary to increase the transconductance g_(m0) of the FET M₂₀. For this purpose, either the current flowing through the FET M₂₀ has to be increased, or the dimension of the FET M₂₀ must be considerably enlarged. However, these methods will cause another problem such as increase of consumed power or chip size. In a typical example, the necessary transconductance was 1 mS. For obtaining such a transconductance, the current of 1.5 mA must flow through the FET M₂₀, or the FET M₂₀ has to have the channel width to length ratio W/L of about 200.

Turning to FIG. 7, there is shown a basic circuit diagram of the operational amplifier in accordance with the present invention. The shown operational amplifier comprises a two-input initial amplifier 1 having the transconductance g_(m1), whose output is connected to a second or output amplifier 2 having the transconductance g_(m2). Further, a capacitor C and a resistor R are series-connected between the outputs of the initial and second amplifiers 1 and 2, in addition to a feedback path consisting of a phase compensating capacitor C_(c), a virtual ground point "a" and a feedback current source supplying a current of C_(c) (dV₀ /dt).

A small-signal equivalent circuit of the operational amplifier shown in FIG. 7 can be expressed as shown in FIG. 8, in which g_(m1) and g_(m2) represent the transconductances of the initial stage FET and the second stage FET, respectively; R₁ and C₁ designate output resistance and capacitance of the initial stage; R₂ and R_(c) show output resistance and capacitance of the second stage; r_(m0) is a resistive component between the virtual ground point "a" and the phase compensating capacitor C_(c) ; and V_(i) and V_(o) and input and output voltages, respectively.

On the basis of the equivalent circuit of FIG. 8, the closed loop gain of the operational amplifier shown in FIG. 7 can be expressed: ##EQU2## where S is a frequency,

    b=R.sub.1 (C.sub.1 +C)+R.sub.2 (C.sub.2 +C+C.sub.c)

     +g.sub.m2 R.sub.1 R.sub.2 (C+C.sub.c)+r.sub.m0 C.sub.c +RC

    c=R.sub.1 R.sub.2 (C.sub.1 C.sub.2 +C.sub.1 C.sub.c +C.sub.1 C+C.sub.2 C)+r.sub.m0 R.sub.2 C.sub.c (C.sub.2 +C)

     +RC(R.sub.1 C.sub.1 +R.sub.2 C.sub.2 +R.sub.2 C.sub.c)g.sub.m2 R.sub.1 R.sub.2 RCC.sub.c

    d=r.sub.m0 R.sub.1 R.sub.2 C.sub.c (C.sub.1 C.sub.2 +C.sub.1 C+C.sub.2 C)+R.sub.1 R.sub.2 RC.sub.1 C(C.sub.2 +C.sub.c)

     +r.sub.m0 R.sub.2 C.sub.c C(R.sub.1 C.sub.1 +R.sub.2 C.sub.2)

    e=r.sub.m0 R.sub.1 R.sub.2 RC.sub.1 C.sub.2 CC.sub.c

As is apparent from the above equation (2), the operational amplifier of FIG. 7 has two zero points Z₁ and Z₂ at frequencies S_(z1) and S_(z2), respectively, which are expressed as follows: ##EQU3##

In addition, first and second poles P₁ and P₂ appear at frequencies S_(p1) and S_(p2), respectively, which are also expressed: ##EQU4##

Examining the equations (3) to (6), if the resistor R and the transconductance g_(m0) are set at suitable values, even if any circuit constants are given for a desired characteristics, the zero point Z₁ can be shifted to an infinite frequency and also the frequency S_(z2) of the second zero point Z₂ can be shifted to be consistent with the frequency S_(p2) of the second pole P₂. If such a shift of the zero points is possible, the adverse effect of the zero points can be perfectly eliminated without increase in consumed power or chip size.

For example, assuming g_(m2) =5 μS, C₁ =0.5 pF, C₂ =1.0 pF, C=3 pF, C_(c) =20 pF, R₁ =10MΩ, R₂ =5MΩ, g_(m0) =30 μS, and R=200KΩ, there are obtained S_(z1) =∞ Hz, S_(z2) =1.5 MKz and S_(p2) =1.5 MHz. In addition, the closed loop gain V₀ /V_(i) can be expressed: ##EQU5##

Incidentally, the frequency S_(p1) of the first pole P₁ is 170 Hz, and third and fourth poles P₃ and P₄ are positioned at such a very high frequencies that cannot have a substantial influence to the operational amplifier.

Next, the SVRR will be reviewed. In this case, even if the resistive component r_(m0) between the virtual ground point "a" and the phase compensating capacitor C_(c) is neglected, the generality of the equivalent circuit is not lost. Therefore, examination will be made on the basis of another equivalent circuit shown in FIG. 9, in which the same elements as those shown in FIG. 8 are given the same Reference signs.

Under this condition, the ratio of a variation ΔV₀ in the output voltage V₀ of the second amplifier 2 to a negative supply voltage variation ΔV_(BB) can be expressed as follows: ##EQU6## where

    b=R.sub.1 (C.sub.1 +C)+R.sub.2 (C.sub.2 +C+C.sub.c)+g.sub.m2 R.sub.1 R.sub.2 (C+C.sub.c)+RC

    c=R.sub.1 R.sub.2 (C.sub.1 C.sub.2 +C.sub.1 C.sub.c +C.sub.1 C+C.sub.2 C)

     +RC(R.sub.1 C.sub.1 +R.sub.2 C.sub.2 +R.sub.2 C.sub.c)+g.sub.m2 R.sub.1 R.sub.2 RCC.sub.c

    d=R.sub.1 R.sub.2 RC.sub.1 C(C.sub.2 +C.sub.c)

    b'=R.sub.1 (C.sub.1 +C)+R.sub.2 (C.sub.2 +C)-g.sub.m2 R.sub.2 (RC+R.sub.1 C.sub.1)+RC

    c'=R.sub.1 R.sub.2 (C.sub.1 C.sub.2 +C.sub.1 C+C.sub.2 C)

     +RC(R.sub.1 C.sub.1 +R.sub.2 C.sub.2)-g.sub.m2 R.sub.1 R.sub.2 RCC.sub.1

    d'=R.sub.1 R.sub.2 RC.sub.1 C.sub.2 C

Therefore, the SVRR can be expressed: ##EQU7##

Furthermore, it can be said from the equation (9) that the SVRR has a substantially flat characteristics within a range from 0 Hz to a frequency f(Hz) which can be expressed: ##EQU8##

Therefore, if the above-mentioned circuit constants are given, the frequency f becomes 180 KHz. Namely, the SVRR is improved by three figures in respect to the first pole frequency S_(p1) of 170 Hz.

The above analysis is directed to the SVRR against to the negative power supply voltage, but a similar result can be also obtained in respect to the SVRR against the positive supply voltage.

Referring to FIG. 10, there is shown a circuit diagram of an operational amplifier embodying the aforementioned principle in accordance with the present invention.

The shown operational amplifier includes an initial stage constituted of a pair of input n-channel FETs M₃₁ and M₃₂ connected in the form of a differential circuit. A gate of the FET M₃₁ forms one input, for example, a non-inverted input of the operational amplifier, and a gate of the other FET M₃₂ constitutes the other input, for example, an inverted input of the amplifier. The pair of input FETs M₃₁ and M₃₂ have their drains connected to a positive supply voltage through n-channel FETs M₃₃ and M₃₄ and p-channel FETs M₃₅ and M₃₆, respectively. The FETs M₃₃ and M₃₄ constitute constant current source, as will be explained hereinafter. The FET M₃₅ and M₃₆ are connected to form an active load in the type of a current mirror circuit. Sources of the FETs M₃₁ and M₃₂ are common-connected to a drain of an n-channel FET M₃₇, which is connected at its source to a negative supply voltage so as to function as a constant current source.

The connection between the FETs M₃₄ and M₃₆ is connected to a gate of an output p-channel FET M₃₈ which constitutes a second or output stage of the operational amplifier. This FET M₃₈ is connected at its source to the positive supply voltage and at its drain to the negative supply voltage through an n-channel FET M₃₉ which functions as an active load in the form of a constant current source explained hereinafter. In addition, the drain of the FET M₃₈ is connected to an output of the operational amplifier, and also connected through a phase compensation feedback capacitor C_(c) to the drain of the input FET M₃₂.

Further, the drain of the FET M₃₈ is connected through another capacitor C and a p-channel FET M₄₀ to the gate of the FET M₃₈ itself. A gate of the FET M₄₀ is connected to a gate and a drain of a p-channel FET M₄₁. A source of the FET M₄₁ is connected to a drain and a gate of a p-channel FET M₄₂ whose source is connected to the positive voltage source. The drain of the FET M₄₁ is connected to the negative voltage source through an n-channel FET M₄₃. Thus, as seen from the above, since the FET M₄₁ and M₄₂ function as resistors, respectively, and since the FET M₄₃ constitutes a constant current source as will be explained hereinafter, the FET M₄₁, M₄₂ and M₄₃ form a bias circuit determining the gate voltage of the FET M₄₀. Therefore, the FET M₄₀ operates as a resistive element.

A constant current source I and an n-channel FET M₄₄ are connected in series across the supply voltages. The FET M₄₄ has a gate thereof connected to the drain of FET M₄₄ itself and also connected to gates of n-channel FETs M₄₅ and M₄₆ and the FETs M₃₇, M₄₃ and M₃₉, so that the FET M₄₀ constitutes an input path of a current mirror circuit and the FETs M₄₅, M₄₆ M₃₇, M₄₃ and M₃₉ form different output paths of the current mirror circuit, respectively, which function constant current sources.

In addition, the FET M₄₅ has a drain thereof connected to a gate and a drain of a p-channel FET M₄₇, whose source is connected to the positive supply voltage. This FET M₄₇ has its gate connected to a gate of another p-channel FET M₄₈ so as to form a current mirror circuit. The FET M₄₈ is connected at its drain to the drain of the FET M₄₆ through two series-connected n-channel FETs M₄₉ and M₅₀. These FETs are short-circuited between their gate and drain so as to function as a resistive element. The gate of the FET M₄₉ is connected to the gates of the FETs M₃₃ and M₃₄. Thus, the FETs M₄₅, M₄₆, M₄₇, M₄₈, M₄₉ and M₅₀ form a bias circuit providing a constant gate voltage to the FETs M₃₃ and M₃₄. Therefore, the FETs M₃₃ and M₃₄ function as constant current sources.

In the operational amplifier as mentioned above, the virtual ground point "a" is provided at the connection between the FETs M₃₂ and M₃₄. The sources of the two FETs M₃₃ and M₃₄ are connected to the virtual ground point "a" through the resistive components 1/g_(m0) of the FETs M₃₃ and M₃₄ having the transconductance g_(m0). However, the adverse effect of the zero point caused by the resistive component 1/g_(m0) of the FETs M₃₃ and M₃₄ is canceled by the second pole made shiftable by the FET M₄₀.

Since this FET M₄₀ is connected in series to the capacitor C, no current will flow through the FET M₄₀. In this connection, the gate bias circuit is provided for the FET M₄₀, but the comsumed current in the bias circuit is on the order of several ten microamperes. In addition, it is sufficient if the FETs M₃₃ and M₃₄ generating the zero point which should be canceled by the second pole produced by the FET M₄₀, has the channel width to length ratio W/L of at least about 10. This means that the current flowing through these FETs is on the order of several ten microamperes.

As seen from the above description, in the present invention, a resistive element and a capacitive element are series-connected between the outputs of the initial and second stages. With this circuit arrangement, the operational amplifier can have an excellent SVRR and phase compensation characteristics with only a small consumed power and required element size.

The invention has thus been shown and described with reference to specific embodiments. However, it should be noted that the invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims. 

I claim:
 1. An operational amplifier which comprises an initial amplifier stage having a pair of inputs, a second amplifier stage connected to an output of the initial stage, a phase compensating capacitive element connected between an output terminal of the second stage and a virtual ground point, and a constant current source connected to the virtual ground point and the output of the initial stage, wherein the improvement comprises a resistive element and a second capacitive element series-connected between the output of the initial stage and the output of the second stage.
 2. An operational amplifier as claimed in claim 1 wherein the resistive element is a field effect transistor and the capacitive element is a capacitor.
 3. An operational amplifier as claimed in claim 1 wherein the initial amplifying stage includes first and second field effect transistors connected in the form of a differential circuit, the gates of the field effect transistors forming the pair of inputs, the field effect transistors having their sources common-connected to a first constant current source circuit which is connected to negative supply voltage, and the field effect transistors having their drains respectively connected through a pair of second constant current source circuits and a pair of first active loads to a positive supply voltage, the connection between one of the second constant current source circuits and the first active load connected in series thereto being connected to the input of the second amplifier stage, the one second constant current source circuit constituting the above mentioned constant current source.
 4. An operational amplifier as claimed in claim 3, wherein the phase compensating capacitive element is a capacitor connected between the output of the second amplifier stage and the one end of the above mentioned one second constant source circuit which is connected at its opposite end to the input of the second amplifier stage.
 5. An operational amplifier as claimed in claim 4 wherein the second amplifier stage includes a third field effect transistor having its gate connected to the connection between the above mentioned one second constant current source and the first active load connected in series thereto, the third field effect transistor being connected at its source to the positive supply voltage and at its drain through a third constant current source to the negative supply voltage, the resistive element and the second capacitive element being connected in series between the gate and the source of the third field transistor.
 6. An operational amplifier as claimed in claim 5 wherein the resistive element is a fourth field effect transistor having a drain-source path connected in series to the second capacitive element, the gate of the fourth field effect transistor being connected to a first gate bias circuit.
 7. An operational amplifier as claimed in claim 6 wherein the first gate bias circuit includes two resistors and a fourth constant current source circuit which are connected in series between the positive and negative supply voltages, the connection between the fourth constant current source circuit and one of the two resistors being connected to the gate of the fourth field effect transistor.
 8. An operational amplifier as claimed in claim 7 wherein each of the two resistors is a field effect transistor having gate and drain common-connected to function as a resistor.
 9. An operational amplifier as claimed in claim 7 wherein each of the second constant current source circuits is formed of a fifth field effect transistor having a drain-source path connected between the corresponding one of the first and second field effect transistors and the associated first active load, the pair of the fifth field effect transistors having their gates common-connected to a second gate bias circuit.
 10. An operational amplifier as claimed in claim 9 wherein the second gate bias circuit includes a fifth constant current source circuit, two resistors and a sixth constant current source circuit which are connected in series in the named order between the positive and negative supply voltages, the connection between the fifth constant current source circuit and one of the two resistors being connected to the gates of the fifth field effect transistors.
 11. An operational amplifier as claimed in claim 10 wherein each of the two resistors in the second gate bias circuit is a field effect transistor having gate and drain common-connected to function as a resistor.
 12. An operational amplifier as claimed in claim 10 further including a main constant current source and a sixth field effect transistor connected in series between the positive and negative supply voltages, the sixth field effect transistor having common-connected gate and drain, and wherein each of the first, third, fourth and sixth constant current source circuits are a field effect transistor having a gate connected to the gate of the sixth field effect transistor.
 13. An operational amplifier as claimed in claim 12 further including seventh and eighth field effect transistors connected in series between the positive and negative supply voltages, the seventh field effect transistor having a gate connected to the gate of the sixth field effect transistor, and wherein the fifth constant current source is a ninth field effect transistor having a gate connected to the gate and drain of the eighth field effect transistors so that the eighth and ninth field effect transistors form a current mirror circuit.
 14. An operational amplifier comprising:first and second field effect transistors connected in the form of a differential circuit and having gates thereof forming a pair of inputs, the field effect transistors having their sources common-connected to a first constant current source which is connected to a negative supply voltage, and the field effect transistors having their drains respectively connected through a pair of second constant current sources and a pair of first active loads to a positive supply voltage; a third field effect transistor having its gate connected to the connection between one of the second constant current sources and the first active load connected in series thereto, the third field effect transistor being connected at its source to the positive supply voltage and at its drain through a third constant current source to the negative supply voltage; a phase compensating capacitor connected between the drain of the third field effect transistor and the one end of the above mentioned one second constant current source which is connected at its opposite end to the gate of the third field effect transistor; and a resistor and a second capacitor connected in series between the gate and the drain of the third field transistor.
 15. An operational amplifier as claimed in claim 14 wherein the resistor is formed of a fourth field effect transistor having a drain-source path connected in series to the second capacitor, the gate of the fourth field effect transistor being connected to a first gate bias circuit.
 16. An operational amplifier as claimed in claim 15 wherein the first gate bias circuit includes two resistors and a fourth constant current source which are connected in series between the positive and negative supply voltages, the connection between the fourth constant current source and one of the two resistors being connected to the gate of the fourth field effect transistor.
 17. An operational amplifier as claimed in claim 16 wherein each of the two resistors is a field effect transistor having gate and drain common-connected to function as a resistor.
 18. An operational amplifier as claimed in claim 16 wherein each of the second constant current sources is formed of a fifth field effect transistor having a drain-source path connected between the corresponding one of the first and second field effect transistors and the associated first active load, the pair of the fifth field effect transistors having their gates common-connected to a second gate bias circuit.
 19. An operational amplifier as claimed in claim 18 wherein the second gate bias circuit includes a fifth constant current source, two resistors and a sixth constant current source which are connected in series in the named order between the positive and negative supply voltages, the connection between the fifth constant current source and one of the two resistors being connected to the gates of the fifth field effect transistors.
 20. An operational amplifier as claimed in claim 19 wherein each of the two resistors in the second gate bias circuit is a field effect transistor having gate and drain common-connected to function as a resistor.
 21. An operational amplifier as claimed in claim 19 further including a main constant current source and a sixth field effect transistor connected in series between the positive and negative supply voltages, the sixth field effect transistor having common-connected gate and drain, and wherein each of the first, third, fourth and sixth constant current sources are a field effect transistor having a gate connected to the gate of the sixth field effect transistor.
 22. An operational amplifier as claimed in claim 21 further including seventh and eighth field effect transistors connected in series between the positive and negative supply voltages, the seventh field effect transistor having a gate connected to the gate of the sixth field effect transistor, and wherein the fifth constant current source is a ninth field effect transistor having a gate connected to the gate and drain of the eighth field effect transistor so that the eighth and ninth field effect transistors form a current mirror circuit. 